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Collaboration diagram for CM3 Core Definitions:</div>
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<center><table><tr><td><img src="group___c_m_s_i_s___c_m3__core__definitions.png" border="0" alt="" usemap="#group______c__m__s__i__s______c__m3____core____definitions"/>
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Modules</h2></td></tr>
<tr class="memitem:group___c_m_s_i_s___c_m3__core__register"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___c_m3__core__register.html">CMSIS CM3 Core Register</a></td></tr>
<tr class="memitem:group___c_m_s_i_s___c_m3___core___function_interface"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___c_m3___core___function_interface.html">CMSIS CM3 Core Function Interface</a></td></tr>
<tr class="memitem:group___c_m_s_i_s___c_m3___core_debug_interface"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___c_m3___core_debug_interface.html">CMSIS CM3 Core Debug Interface</a></td></tr>
<tr><td colspan="2"><h2><a name="define-members"></a>
Defines</h2></td></tr>
<tr class="memitem:gac1c1120e9fe082fac8225c60143ac79a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#gac1c1120e9fe082fac8225c60143ac79a">__CM3_CMSIS_VERSION_MAIN</a>&#160;&#160;&#160;(0x01)</td></tr>
<tr class="memitem:ga9ff7a998d4b8b3c87bfaca6e78607950"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga9ff7a998d4b8b3c87bfaca6e78607950">__CM3_CMSIS_VERSION_SUB</a>&#160;&#160;&#160;(0x30)</td></tr>
<tr class="memitem:gaf888c651cd8c93fd25364f9e74306a1c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf888c651cd8c93fd25364f9e74306a1c">__CM3_CMSIS_VERSION</a>&#160;&#160;&#160;((<a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#gac1c1120e9fe082fac8225c60143ac79a">__CM3_CMSIS_VERSION_MAIN</a> &lt;&lt; 16) | <a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga9ff7a998d4b8b3c87bfaca6e78607950">__CM3_CMSIS_VERSION_SUB</a>)</td></tr>
<tr class="memitem:ga63ea62503c88acab19fcf3d5743009e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga63ea62503c88acab19fcf3d5743009e3">__CORTEX_M</a>&#160;&#160;&#160;(0x03)</td></tr>
<tr class="memitem:gae3fe3587d5100c787e02102ce3944460"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>&#160;&#160;&#160;4</td></tr>
<tr class="memitem:gaf63697ed9952cc71e1225efe205f6cd3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>&#160;&#160;&#160;volatile const</td></tr>
<tr class="memitem:ga7e25d9380f9ef903923964322e71f2f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga7e25d9380f9ef903923964322e71f2f6">__O</a>&#160;&#160;&#160;volatile</td></tr>
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</table>
<hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
<p>This file defines all structures and symbols for CMSIS core:</p>
<ul>
<li>CMSIS version number</li>
<li>Cortex-M core registers and bitfields</li>
<li>Cortex-M core peripheral base address </li>
</ul>
<hr/><h2>Define Documentation</h2>
<a class="anchor" id="gaf888c651cd8c93fd25364f9e74306a1c"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define <a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf888c651cd8c93fd25364f9e74306a1c">__CM3_CMSIS_VERSION</a>&#160;&#160;&#160;((<a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#gac1c1120e9fe082fac8225c60143ac79a">__CM3_CMSIS_VERSION_MAIN</a> &lt;&lt; 16) | <a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga9ff7a998d4b8b3c87bfaca6e78607950">__CM3_CMSIS_VERSION_SUB</a>)</td>
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<p>CMSIS HAL version number </p>

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<a class="anchor" id="gac1c1120e9fe082fac8225c60143ac79a"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define <a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#gac1c1120e9fe082fac8225c60143ac79a">__CM3_CMSIS_VERSION_MAIN</a>&#160;&#160;&#160;(0x01)</td>
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<p>[31:16] CMSIS HAL main version </p>

</div>
</div>
<a class="anchor" id="ga9ff7a998d4b8b3c87bfaca6e78607950"></a>
<div class="memitem">
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          <td class="memname">#define <a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga9ff7a998d4b8b3c87bfaca6e78607950">__CM3_CMSIS_VERSION_SUB</a>&#160;&#160;&#160;(0x30)</td>
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<div class="memdoc">
<p>[15:0] CMSIS HAL sub version </p>

</div>
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<a class="anchor" id="ga63ea62503c88acab19fcf3d5743009e3"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define <a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga63ea62503c88acab19fcf3d5743009e3">__CORTEX_M</a>&#160;&#160;&#160;(0x03)</td>
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<p>Cortex core </p>

</div>
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<a class="anchor" id="gaf63697ed9952cc71e1225efe205f6cd3"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define <a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>&#160;&#160;&#160;volatile const</td>
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<p>IO definitions</p>
<p>define access restrictions to peripheral registers defines 'read only' permissions </p>

</div>
</div>
<a class="anchor" id="gaec43007d9998a0a0e01faede4133d6be"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define <a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a>&#160;&#160;&#160;volatile</td>
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<div class="memdoc">
<p>defines 'read / write' permissions </p>

</div>
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<a class="anchor" id="gae3fe3587d5100c787e02102ce3944460"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define <a class="el" href="group___l_p_c17xx___system.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>&#160;&#160;&#160;4</td>
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<div class="memdoc">
<p>standard definition for NVIC Priority Bits </p>

</div>
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<a class="anchor" id="ga7e25d9380f9ef903923964322e71f2f6"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define <a class="el" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga7e25d9380f9ef903923964322e71f2f6">__O</a>&#160;&#160;&#160;volatile</td>
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<div class="memdoc">
<p>defines 'write only' permissions </p>

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